Intel's new MESO spintronics device architecture offers dramatic improvements over current CMOS devices

Researchers from Intel and the University of California in Berkeley developed a new scalable spintronics logic deice, which they magneto-electric spin-orbit (MESO) logic device that offers dramatic improvement over current CMOS technology.

MESO architecture, Intel & UCB

Intel says that MESO based logic, compared to CMOS, will offer a superior switching energy (by a factor of 10 to 30), lower switching voltage (by a factor of 5), an enhanced logic density (by a factor of 5) and ultra low standby power (due to the non-volatility of the spin-based device).

Intel: we'll have to adopt fundamentally new transistor technologies in 4-5 years, Spintronics is a leading candidate

Intel's technology and manufacturing group leader, William Holt, says that if Intel wants to keep improving its chips, it will soon have to start using fundamentally new technologies. The company does not know which technology will be adopted, but there are two possible candidates at this stage - Spintronics, and tunneling transistors.

William says that the new technologies will have to be commercialized in four to five years (when Intel moves over to 7-nm production, which is thought to be the limit of silicon transistors), and will initially be used alongside silicon transistors. Intel says we'll need to stop expecting chips to be faster - as the new technologies will mostly benefit the energy efficiency rather than the speed of Intel's future chips.

Intel and Georgia Tech developed a modeling platform to advance spintronics interconnect research

Georgia Institute of Technology, in collaboration (and sponsorship) from Intel developed a physics-based modeling platform that advances spintronics interconnect research for next-generation computing.

The researchers are focusing on developing spintronics switches with adequate connectivity. They are researching the communicating between spin-logic devices and they demonstrated that interconnects are an even more important challenge for beyond-CMOS switches.

SRC and DARPA grant $28 million to open a new Spintronics research center

The Semiconductor Research Corporation, and the Defense Advanced Research Projects Agency (DARPA) has awarded a $28 million five-year grant to open the Center for Spintronic Materials, Interfaces, and Novel Architectures, or C-SPIN. This is a multi-university and industry research center that aims to develop technologies for spin-based computing and memory systems. C-SPIN's research areas include perpendicular magnetic materials, spin channel materials (including topological insulators, monolayer MoS2 and graphene), spintronic interface engineering, spin devices and interconnects and spintronic circuits and architectures.

University partners include the University of Minnesota-Twin Cities, Carnegie Mellon University, Cornell University, MIT, Johns Hopkins University and the University of California, Riverside. Industry partners include IBM, Applied materials, Intel, Texas Instruments and Micron.

Intel's new neuromorphic chip design uses multi-input lateral spin valves and memristors

Intel is proposing a new neuromorphic chip design concept that uses multi-input lateral spin valves (LSV) and memristors. Using these two devices in a cross-bar switch lattice, one can build a neuromorphic CPU. The LSVs are the neurons and the memristors are the synapses.

Theoretically such a chip could hold buillions of neurons and synapses and operate in the in the gigahertz or terahertz range. The device will also be quite efficient - about 300 times more efficient than CMOS equivalents.