CMOS-integrated spintronic p-bit demonstrated on silicon chip
Researchers from Tohoku University and NIST have demonstrated a CMOS-integrated spintronic probabilistic bit (p-bit), marking a significant step toward scalable probabilistic computing hardware. The work experimentally validates a key building block for p-computers by combining superparamagnetic tunnel junctions (sMTJs) with a standard 130 nm CMOS process, enabling stochastic operation directly on a silicon chip.
(a) Photograph of test chips fabricated on a silicon substrate using semiconductor integrated circuit manufacturing processes. (b) Schematic cross-sectional structure of the spintronic p-bit. Transistors and lower interconnect layers were fabricated at SkyWater Technology, followed by fabrication of the spintronic devices at the Research Institute of Electrical Communication, Tohoku University. (c,d) Cross-sectional and plan-view electron microscope images of the spintronic device designed to exhibit stochastic fluctuations. Image from: Tohoku University website
Probabilistic computing targets problems that require efficient exploration of vast solution spaces, such as combinatorial optimization and machine learning. Unlike conventional binary systems, which process deterministic 0 or 1 states, p-bits fluctuate continuously between these states. This stochastic behavior allows p-computers to sample many configurations in parallel, making them well suited for complex optimization tasks.

