Grandis

Researchers at the National University of Singapore (NUS), led by Assistant Professor Ahmet Avsar of the university's Centre for Advanced 2D Materials, have combined a record-fidelity graphene spin-transport platform with magnetic-proximity band engineering to move graphene closer to practical spin-logic and spin-memory devices, across two complementary studies. The work targets one of graphene spintronics' core limitations: interfacial disorder at the electrical contacts that inject and detect spin, which has historically scrambled spin information before it can be read out electrically.

The first study rebuilt the graphene spin-device fabrication process around an inert-glovebox van der Waals assembly, laminating and cleaning the stack to produce atomically flat hexagonal boron nitride (h-BN) tunnel barriers rather than the oxide barriers more commonly used in graphene spin valves. That interface quality translated directly into device performance: nonlocal spin signals reached up to 1.6 kΩ at 2.5 K, spin polarization approached 90% (89% in the lead device), spin lifetime measured about 2.04 nanoseconds with a spin diffusion length of about 4.74 μm, and gate-tunable magnetoresistance exceeded 80%. Critically for eventual device use, the effect persisted at room temperature, where the same device retained a nonlocal spin resistance of about 160 Ω and roughly 42% spin polarization.

UCLA has received a $8.4 million grant from DARPA to research ultra-low-power, non-volatile logic technologies. This is the same DARPA project that also awarded a contract to Grandis on the same subject a couple of weeks ago.

The UCLA researchers are aiming to develop a prototype non-volatile logic circuit, which could lead to the development of new classes of ultra–low-power, high-performance electronics. The research program will explore three technical areas: the behavior of nanoscale magnetic materials; the fabrication and testing of a non-volatile logic circuit; and the development of novel circuits and circuit-design tools.

The project will be managed at UCLA by research associate Pedram Khalili and will be led under principal investigators Kang Wang and Alex Khitun. It will involved researchers from UCLA, UC Irvine, Yale University and the University of Massachusetts.

Grandis has been awarded a new contract from DARPA to use their spintronics and magnetic-material expertise and develop non-volatile spin logic applications: which promises non-volatile, ultra-fast, radiation-hard and radically lower power consumption.

Development work will focus on integrating magnetic tunnel junction (MTJ) materials capable of sensing very small magnetic fields with nano-magnets performing logic operations. The goal is to demonstrate non-volatile spin logic circuits operating at ultra-fast speeds of less than 1 nanosecond and ultra-low power consumption of less than 10 atto-Joules per operation. Such performance coupled with the inherent non-volatility of spin logic devices will enable not just significant reductions in the active power consumption of microprocessors but also the virtual elimination of standby power consumption.

Grandis announced that it has been awarded $6.0 million from the Defense Advanced Research Projects Agency (DARPA) for the initial phase of research to develop spin-transfer torque random access memory (STT-RAM) chips (for the 45 nm technology node and beyond). The total value of the effort, if all phases of the development program are completed, could be up to $14.7 million over four years.