Researchers from at Southern University of Science and Technology, Xi'an Jiaotong University and other institutes recently reported a spintronic compute-in-memory (CIM) macro designed to improve computational efficiency in artificial intelligence hardware. The device is a 64-kb non-volatile digital CIM macro fabricated using 40-nm spin-transfer torque magnetic random-access memory (STT-MRAM) technology, which stores information through the magnetic orientation of nanometer-scale layers.
Conventional computing architectures separate memory and processing units, requiring frequent data transfer that increases latency and energy consumption. CIM designs address this limitation by integrating storage and computation, though most prior implementations have relied on analog operations that constrain accuracy, scalability, and robustness. The newly developed digital CIM architecture addresses these limitations by combining the endurance and non-volatility of STT-MRAM with digitally controlled computation.
The macro implements in situ multiplication and digitization at the bitcell level, together with precision-reconfigurable digital addition and accumulation at the macro level. A toggle-rate-aware training scheme is introduced to manage device-level variations during algorithm optimization. The system supports matrix–vector multiplications with flexible input and weight precision levels of 4, 8, 12, and 16 bits, maintaining software-equivalent inference accuracy for both residual networks and physics-informed neural networks at respective 8-bit and 16-bit precision.
Experimental characterization shows that the macro achieves computation latencies between 7.4 ns and 29.6 ns, and energy efficiencies ranging from 7.02 to 112.3 tera-operations per second per watt across precision modes. These results demonstrate the viability of digital spintronic CIM designs for low-latency, high-efficiency AI computation.
The work illustrates the potential of spintronic memory technologies as scalable building blocks for digital compute-in-memory systems. Integration of such components could facilitate on-device AI inference with reduced power consumption and minimal dependency on external data centers.