Researchers from the National University of Singapore (NUS), together with collaborators from the University of Messina, Istituto Nazionale di Geofisica e Vulcanologia, the Indian Institute of Technology Madras, Politecnico di Bari and Peking University, have reported two spintronic probabilistic computing systems that accelerate combinatorial optimization while cutting energy consumption. The work, led by Prof. Yang Hyunsoo of the NUS Department of Electrical and Computer Engineering, was published as a pair of papers.
Both systems are built around magnetic tunnel junctions (MTJs) operated deliberately in their stochastic regime. Rather than treating thermal fluctuations as a source of error to be suppressed, the devices are used as compact, tunable true random number generators - the physical substrate for probabilistic bits.
In the first paper, the team built a probabilistic Ising processor for all-to-all connected quadratic assignment problems, a notoriously demanding class of optimization problem. The system integrates 144 compact spintronic tunable RNGs in a massively parallel architecture, reaching a Monte Carlo sampling throughput of 14.4 million flips per second. Paired with a co-designed parallel trial annealing scheme, the integrated system achieved a 123-fold speedup with 98.3% energy savings over conventional Gibbs sampling, and a 3.2-fold speedup with 58.3% energy savings relative to a CPU implementation.
Notably, the researchers also benchmarked their hardware directly against state-of-the-art D-Wave quantum annealers. Across the tested quadratic assignment dataset, the spintronic processor consistently returned feasible, high-quality solutions, while the quantum annealers struggled to produce feasible results as problem size grew.
The second paper scales the concept further, demonstrating a fully connected probabilistic Ising machine based on 250 spin-transfer-torque MTJs interfaced with an FPGA. Because the architecture updates spins in parallel, the team could apply a cluster parallel update method that sidesteps the serial bottleneck of Gibbs sampling on sparsely connected graphs - worth a 10-fold acceleration with no hardware changes. The group also showed experimentally that simulated quantum annealing improved solution quality by a factor of 20 over conventional simulated annealing, while making the machine more tolerant of device-to-device variability.
According to Prof. Yang, quantum computing remains a compelling long-term direction, but many optimization workloads need solutions today - and spintronic probabilistic computing offers gains in speed, energy efficiency and solution quality on a platform much closer to deployment. First author Shuhan Yang, a PhD student at NUS, framed the underlying idea as treating randomness as a computing resource rather than a defect.
Looking ahead, the team plans to scale the hardware further and explore chiplet-based architectures for large-scale probabilistic computing, with potential applications in AI, logistics, scheduling, financial modeling, communications and electronic design automation.