Researchers from Tohoku University and NIST have demonstrated a CMOS-integrated spintronic probabilistic bit (p-bit), marking a significant step toward scalable probabilistic computing hardware. The work experimentally validates a key building block for p-computers by combining superparamagnetic tunnel junctions (sMTJs) with a standard 130 nm CMOS process, enabling stochastic operation directly on a silicon chip.
(a) Photograph of test chips fabricated on a silicon substrate using semiconductor integrated circuit manufacturing processes. (b) Schematic cross-sectional structure of the spintronic p-bit. Transistors and lower interconnect layers were fabricated at SkyWater Technology, followed by fabrication of the spintronic devices at the Research Institute of Electrical Communication, Tohoku University. (c,d) Cross-sectional and plan-view electron microscope images of the spintronic device designed to exhibit stochastic fluctuations. Image from: Tohoku University website
Probabilistic computing targets problems that require efficient exploration of vast solution spaces, such as combinatorial optimization and machine learning. Unlike conventional binary systems, which process deterministic 0 or 1 states, p-bits fluctuate continuously between these states. This stochastic behavior allows p-computers to sample many configurations in parallel, making them well suited for complex optimization tasks.
At the device level, the demonstrated p-bit relies on an sMTJ whose resistance fluctuates due to thermal magnetic noise in a superparamagnetic regime. These resistance fluctuations are converted into a time-varying digital output voltage through CMOS circuitry. Crucially, the probability distribution of the output is tunable: by adjusting the input bias voltage, the time-averaged output can be shifted between predominantly 0 and predominantly 1, while maintaining stochastic switching.
The fabrication approach combines semiconductor and spintronic processes across two sites. Transistors and lower interconnect layers were produced using a 130 nm CMOS platform from SkyWater Technology, while the superparamagnetic nanodevices and upper metal layers were integrated at Tohoku University. This monolithic integration demonstrates compatibility with established semiconductor manufacturing, addressing a key scalability challenge for sMTJ-based systems.
Experimentally, the team confirmed two defining characteristics of p-bit operation:
- Continuous stochastic fluctuations in the output voltage over time.
- Electrical tunability of the output probability via the input voltage.
The resulting unit cell shows that intrinsic magnetic randomness in nanoscale devices can be harnessed and controlled within standard CMOS circuitry. This integration eliminates the need for externally assembled components, paving the way for dense, large-scale probabilistic circuits.
By establishing a CMOS-compatible platform for spintronic p-bits, the work provides a practical route toward scaling p-computers beyond current prototype systems. With further advances in device uniformity, circuit design, and integration density, such architectures could enable efficient hardware implementations for emerging applications in AI and machine learning.