Tohoku University - Page 3

NEC and Tohoku's University have jointly developed a new spintronics-based logic prototype chip specifically aimed towards text search systems. Early testing suggest that this new chip has drastically reduced power consumption - 1% or even less compared to conventional systems (DRAM and CPU). This significant reduction was achieved due to the non-volatility of the spintronic circuit which only requires power to necessary circuit blocks and does not require any standby power.

NEC and Tohoku developed new multi-functional CAM cells for text-search logic. The new CAM cells are able to avoid searching for long index texts when searching for short lengths of text within a large amount of index data. This was achieved by setting up combinations (patterns) of input signals that represent long texts. This enables circuits to detect when a long text is input, and to avoid any further unnecessary operations.

Researchers from Tohoku University have shown that electron spins can be preserved for long distances using optimized organic compounds. This is because organic compounds are made mostly from carbon, in which the spin–orbit interaction is quite small. Using fullerene (C60) films the researchers made devices in which electrons traveled up to 110 nm at room temperature while preserving their spin.

The researchers used fullerence because there's no hydrogen in it (common in other organic materials) and this helps reduce the hyper fine interactions between electron and nuclear spins that can induce spin-flipping events. They built an organic spin valve in which two ferromagnetic electrons are placed in contact with an organic layer.

Tohoku University and NEC developed new "zero standby power" Spintronics logic ICs. They actually developed a library that establishes automatic design flow of nonvolatile logic-in-memory integrated circuits. Using this library they managed to design and make a prototype image processing chip that reduces "unnecessary power consumption" by up to 75%.

This new chip uses 25 processors, but by running only the needed processors for each operation and turning off the power for the unused ones, the power consumption is reduced. NEC says that the new library can be used in addition to existing design tools and will enable large-scale logic-in memory integrated circuits, even without expertise in circuit design or Spintronics technology.

Makoto Kohda from the Tohoku University gave a special presentation titled "electronic spin polarization in semiconductor nanostructures". In his talk Makoto discusses spin-polarized current generation without external magnetic fields or ferromagnets (by using Stern-Gerlach spin separation in semiconductor nanostructures). The talk outline is fundamental technologies for Spintronics, spin-dependent force for spin generation/detection, quantum point contact (QPC) for inducting spin polarization, temperature stability for spin polarization in QPC and quantitative evaluation of spin polarization by shortnoise.

This presentation was given at Keio University's Semiconductor-Spintronics workshop which took place on January 24.

Hideo Ohno from Tohoku University's center for spintronics integrated systems gave a special presentation titled "recent topics in diluted magnetic semiconductors". In his talk, Hideo gives an introduction to ferromagnetic (III,Mn)As and then discusses manipulation by electric-field and materials systems other than (III,Mn)As.

This presentation was given at Keio University's Semiconductor-Spintronics workshop which took place on January 24.

NEC and Tohoku University have developed a new technology that aims to improving the reliability of spintronics logic integrated circuits. This could lead to devices that have a standby power of zero. They have verified this new technology on a prototype chip.

NEC and Tohoku's new device structure connects spin elements in a series, which prevents power consumption from increasing and prevents the area of the circuit from becoming larger. These highly reliable circuit components also support automatic placement and wiring, which means that highly reliable non-volatile logic integrated circuits can be designed even without expertise in spintronics technology.

Professor Hideo Ohno from the Laboratory of Nanoelectronics and Spintronics, at Tohoku University is this year's IEEE David Sarnoff Award winner, a very prestigious award. Professor Ohno was in contention for this year's Nobel prize in physics. Here's a 2010 video showing Ohno's group work on integrated circuits using spintronics:

Tohoku University and Tokyo Electron announced that they will jointly develop Spintronics memory integration and manufacturing technology. Professor Tetsuo Endoh from Tohoku's Center for Spintronics Integrated Systems (CSIS) will lead the research. The aim of this project is to present a miniature highly-integrated Spintronics memory device and the process technologies needed to commercially manufacture it.

The CSIS is considered one of the world's leaders in Spintronics memory, and will contribute its magnetic material technologies, device technologies and design technologies. TEL will contribute process and equipment technologies. The video above shows the Spintronics IC work done at the CSIS.

Here's a video explaining the Masafumi Shirai Laboratory at Tohoku University?theoretical research on electrical conductivity in magnetoresistive devices. The aim is to achieve very functional spintronics devices using highly spin-polarized materials:

A group led by Professor Hideo Ohno in the Laboratory of Nanoelectronics and Spintronics, at Tohoku University is working to develop new integrated circuits using spintronics. The ICs store data in nonvolatile memory using magnetism (MRAM), so their standby power can be made zero. This memory utilizes the tunnel magneto-resistance effect.